(a) Field of the Invention
The present invention relates to a semiconductor device operating in an active mode and a standby mode and, more particularly, to a semiconductor device capable of shifting from the standby mode to the active mode at a higher speed.
(b) Description of the Related Art
Some semiconductor devices operate in an active mode (normal operation mode) and a standby mode. The standby mode reduces the power dissipation of the semiconductor device, whereas the active mode allows transistors installed in the semiconductor device to operate with a designed performance. The switching between the active mode and the standby mode may be achieved by controlling the substrate potential (Vb) of the transistors. However, it is known in this technique that, if only the substrate potential Vb is raised in the transistors having a reduced device size, a leakage current referred to as gate-induced-drain leakage current may flow to thereby increase the power dissipation in the standby mode. Patent Publication JP-2000-357962A describes a technique for solving the above problem.
FIG. 9 shows the configuration of the semiconductor device described in JP-2000-357962A. The semiconductor device 200 includes transistors P201, P202, N201 and N202, referred to as target transistors hereinafter, for which the substrate potential and source potential are controlled, substrate-potential generation circuits 211 and 214, and source-potential generation circuits 212 and 213. The substrate-potential generation circuits 211 and 214 generate a potential to be supplied to power source lines 221 and 224, whereas the source-potential generation circuits 212 and 213 generate a potential to be supplied to power source lines 222 and 223. In this text, the N and P attached to the reference numeral of the transistors means the conductivity type of the transistors, indicating n-channel transistor and p-channel transistor, respectively.
The source (source region) of target transistors P201, P202, N201 and N202 is connected to a power source line 222 or 223. The well or substrate of target transistors P201, P202, N201, and N202 is connected to power source line 221 or 224. Target transistors P201 and N201 as well as target transistors P202 and N202, for which the substrate potential is to be controlled, configure an inverter, for example, which outputs a signal based on the signal input to the gate electrode.
The semiconductor device 200 allows the inverter to operate in the active mode by using the power source supplied between a high-potential(-side) power source VPERI supplied to internal power source lines 221 and 222 and a low-potential-side power source VSS supplied to internal power source lines 223 and 224. The internal power source VPERI is obtained by lowering the potential of the external high-potential power source VDD. Since the threshold voltage (Vt) of the transistors configuring the inverter is set at as low as 0.2V, for example, the transistors may have a sub-threshold leakage current flowing therethrough even when the input signal Vg supplied to the inverters is fixed at the ground level, i.e., VSS level, in the standby mode. In addition, a small leakage current flows through the target transistors in a standby state due to the floating potential of the power source line (VSS) or gate electrode, generation of noise, and influence by the range of variation in the threshold voltage caused by a manufacturing process, etc. In particular, an increase of the operating current caused by the leakage current incurs a problem especially in a large-scale semiconductor device.
In order to reduce the above leakage current in the standby mode of the semiconductor device, substrate-potential generation circuit 211 provides a substrate potential to target transistors P201 and P202, which is higher than the substrate potential VPERI provided in the active mode, whereas source-potential generation circuit 212 provides a source potential to target transistors P201 and P202, which is lower than the source potential VPERI in the active mode. In addition, in the standby mode, substrate-potential generation circuit 214 provides a substrate potential to target transistors N201 and N202, which is lower than the substrate potential VSS provided in the active mode, whereas source-potential generation circuit 213 provides a source potential to target transistors N201 and N202, which is lower than the source potential VSS provided in the active mode. Due to the above configuration, the gate potential with respect to the source potential of the target transistors allows the target transistors to shift in a direction toward a turn-OFF state thereof, and the substrate potential acts to increase the threshold voltage of the transistors, whereby the leakage current, which may otherwise flow due to the gate potential slightly exceeding the threshold voltage, as well as the sub-threshold leakage current can be suppressed, to thereby reduce the power dissipation.
FIG. 10 is a waveform diagram showing the potential of the power source lines 221-224. In the active mode, substrate-potential generation circuit 211 and source-potential generation circuit 212 both for the p-channel transistors output internal power source potential VPERI generated by lowering the potential of the external power source, whereby the potential Vbp, Vsp of power source line 221, 222 is VPERI. Source-potential generation circuit 213 and substrate-potential generation circuit 214 both for the n-channel transistors output an internal low-potential power source potential VSS, whereby the potential Vsn, Vbn of power source line 223, 224 is VSS. In the active mode, target transistors P201, P202, N201 and N202 operate on the power source (VPERI, VSS) generated by the source-potential generation circuit 212, 213.
During a mode shift from the active mode to the standby mode, substrate-potential generation circuit 211 for the p-channel transistors raises the potential supplied to power source line 221 from a VPERI level by ΔVbn, whereas substrate-potential generation circuit 214 for the n-channel transistors lowers the potential supplied to power source line 224 from a VSS level by ΔVsp. At the same time, substrate-potential generation circuit 212 for the p-channel transistors lowers the potential supplied to power source line 222 from a VPERI level by ΔVbn, whereas substrate-potential generation circuit 213 for the n-channel transistors raises the potential supplied to power source line 223 from VSS level by ΔVsn. Due to the potential modification as described above, the gate potential with respect to the source potential of the target transistors is controlled to allow the target transistors to shift in a direction toward a turn-OFF state thereof, whereby the leakage current of the target transistors is reduced in addition to the reduction due to the shift of the substrate potential.
During a mode shift from the standby mode to the active mode, substrate-potential generation circuit 211 and source-potential generation circuit 212 both for the p-channel transistors return the potential of power source lines 221 and 222 from Vbp, Vsp to a VPERI level, whereas source-potential generation circuit 213 and substrate-potential generation circuit 214 both for n-channel transistors return the potential of power source lines 223 and 224 from Vsn, Vbn to a VSS level. Since the potential output from substrate-potential generation circuit 211 and source-potential generation circuit 212 assumes a VPERI level, the potential Vbp of power source line 221 gradually falls toward VPERI and the potential Vsp of power source line 222 gradually rises toward the VPERI level. In addition, since the potential output from source-potential generation circuit 213 and substrate-potential generation circuit 214 assumes a VSS level, the potential Vsn of power source line 223 gradually falls toward the VSS level and the potential Vbn of power source line 224 gradually rises toward the VSS level. Thus, when the potential Vbp, Vsp of power source lines 221 and 222 assume the VPERI level, and the potential Vsn, Vbn of power source lines 223 and 224 assumes the VSS level, an active mode is restarted.
In the above semiconductor device 200, there is a problem in that the speed at which the potential of power source lines 221 and 222, i.e., the substrate potential and source potential of p-channel target transistors returns to the VPERI level is low during the mode shift from the standby mode to the active mode. Similarly, the speed at which the potential of power source lines 223 and 224, i.e., the source potential and substrate potential of the n-channel target transistors returns to the VSS level is low. In addition, since substrate-potential generation circuits 211 and 214 and source-potential generation circuits 212 and 213 are provided as separate power source circuits, the relationship between the source potential and the substrate potential of the transistors may cause a forward current across the p-n junction during the transient state of the power source potentials, thereby incurring a latch up failure. Further, since power source lines 222 and 223 for providing the source potential is scarcely involved with parasitic well capacitance, a compensating capacitor may be needed to power source lines 222 and 223 for enhancing the source power, which may increase the circuit scale.